Technical Field
This Patent Disclosure relates generally to phase-locked loop systems.
Related Art
A phase-locked loop (PLL) circuit establishes a frequency/phase control loop around a VCO (voltage, or current, controlled oscillator), providing a Vctrl control voltage to adjust VCO frequency/phase to lock the VCO output to the frequency/phase of an input signal, such as a reference frequency signal.
CMOS-based VCO designs commonly use LC and Ring based VCOs. LC VCOs rely on a varactor to fine tune the Vctrl voltage, and commonly include a switching capacitor array/bank to extend the tuning range (extend Kvco gain).
The frequency range within which a PLL circuit can provide a locked output varies with the operation temperature of the PLL circuit, so that a PLL circuit may be unable to remain locked when the operation temperature fluctuates outside a specified temperature range (junction temperature). Two approaches to increasing lock range are increasing varactor size, and increasing the dynamic range of the Vctrl voltage. Increasing varactor size increases Kvco, which leads to an increase in phase noise. Increasing Vctrl can be restricted by varactor stress (reliability) considerations.
While this Background information references in particular an LC VCO, the Disclosure is more generally directed to VCOs with switched capacitor tuning.